Modelling Communication in Message-Passing MIMD Computers
The communication bottleneck in parallel computers is an acknowledged
limitation for reaching performance goals. Current research which
focuses on reducing these limitations has given rise to two problems:
proposed solutions which increase performance often increase costs and
lack of comparability in performance models due to simplifying or
restricting assumptions.
In this work, the major goal is to establish a flexible model
structure, providing cost and performance analysis. To this end, a
hierarchical modular structure, parameterised by design issues at the
top-level and including synthesised HDL modules at the bottom-level is
being developed.
Last modified: Thu Mar 13 15:56:43 MET DST 1997